Integrating a-d conversion system

ABSTRACT

An integrating A-D conversion system which is adapted to provide an analog input voltage in the form of a binary number and comprises the steps of (1) positively integrating a positive analog input voltage for a period of time 2T, (2) subtracting from the resulting voltage in (1) a negative voltage produced by integrating a negative reference voltage -Vr for a period of time T, (3) adding the resulting voltage in (2) with a negative (or positive) voltage produced by integrating the voltage -Vr (or +Vr) for a period of time T/2 according as the resulting voltage in (2) is positive (or negative), (4) adding the resulting voltage in (3) with a negative (or positive) voltage produced by integrating the voltage -Vr (or +Vr) for a period of time T/4 according as the resulting voltage in (3) is positive (or negative), (5) adding the resulting voltage in (4) with a negative (or positive) voltage produced by integrating the voltage -Vr (or +Vr) for a period of time T/8 according as the resulting voltage in (4) is positive (or negative), (6) adding the resulting voltage in (5) with a negative (or positive) voltage produced by integrating the voltage -Vr (or +Vr) for a period of time T/16 according as the resulting voltage in (5) is positive (or negative), . . . . and so on, and obtaining a digital output, representing a binary number whose digits are determined by whether the corresponding resulting voltages in (2), (3), . . . . are positive or negative respectively.

United States Patent @191 Etc 1 INTEGRATING A-D CONVERSION SYSTEM [76] Inventor: Tetutaro Eto, No. 841, 2-chome,

Soshigaya, Tokyo, Japan 22 Filed: Oct. 5, 1972 21 Appl. No.: 295,186

Related US. Application Data [63] Continuation of Ser. No 84,365, Oct. 27, 1970,

abandoned.

[30] Foreign Application Priority Data Primary ExaminerRaulfe B. Zache Assistant ExaminerJoseph M. Thesz, Jr. Attorney, Agent, or Firm--Marshall & Yeasting [57] ABSTRACT An integrating A-D conversion system which is UA- uz.

TlMING SIGNAL GENERATOR Sept. 3, 1974 adapted to provide an analog input voltage in the form of a binary number and comprises the steps of (1) positively integrating a positive analog input voltage for a period of time 2T, (2) subtracting from the resulting voltage in (l) a negative voltage produced by integrating a negative reference voltage V, for a period of time T, (3) adding the resulting voltage in 2) with a negative (or positive) voltage produced by integrating the voltage V, (or +V,) for a period of time T/2 according as the resulting voltage in (2) is positive (or negative), (4) adding the resulting voltage in (3) with a negative (or positive) voltage produced by integrating the voltage V, (or +V,) for a period of time T/4 according as the resulting voltage in (3) is positive (or negative), (5) adding the resulting voltage in (4) with a negative (or positive) voltage produced by integrating the voltage V, (or +V,) for a period of time T/8 according as the resulting voltage in ('4) is positive (or negative), (6) adding the resultingvoltage in (5) with a negative (or positive) voltage produced by integrating the voltage -V (or +V,) for a period of time T/l6 according as the resulting voltage in (5) is positive (or negative), and so on, and obtaining a digital output, representing a binary number whose digits are determined by whether the corresponding resulting voltages in (2), (3), are positive or negative respectively.

3 Claims, 7 Drawing Figures INDICATOR BUFFER mmww 31w 3.833.902

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PAIENTEB 31974 3.833.902 SHE! 7N T REFERENCE v F I G 7 VOLTAGE COMPA RATO R 2 D REFERENCE M VOLTAGE INDICATOR BUFFER 1 UE UC TIMING SIGN AL GENERATOR 1 INTEGRATING A-D'CONVERSION SYSTEM This is a continuation of application Ser. No. 84,365, filed- Oct. 27, 1970, and now abandoned.

BACKGROUND OF THE INVENTION 1. Field of the Invention This invention relates to an A-D conversion system, and more particularly to an integrating A-D conversion system which is adapted to provide an analog input voltage in the form of a digital output having us digits of the binary system.

SUMMARY OF THE INVENTION This invention is to provide a novel integrating A-D conversion method which is adapted to convert an analog voltage into a digital output in the form of a a binary number having n digits. According to this invention,

digital outputs are easily obtained in the form of a binary number through the use of a simple structure ernploying one integrating means.-

BRIEF DESCRIPTION OF THE DRAWING DESCRIPTION OF THE PREFERRED EMBODIMENTS A description will be given first of the example of this invention depicted in FIG. 1. In the figure reference numeral 1 indicates an analog voltage source, from which a positive analog voltage +V,,, is applied to the input side of an amplifier 4 through a resistor 2 having a resistance value R and a fixed contact b and a movable contact c of a switching circuit 3. A capacitor Shaving a capacitance C is connected between the input and output sides of the amplifier 4 and at the output side of the amplifier 4 there is derived an integrated output produced by positively integrating the analog voltage +V,,, with the resistor 2-and the capacitor 5 being used as integration constants.

Reference numeral 7 designates a reference voltage source, from which a positive reference voltage +V, is

supplied to the input side of the amplifier 4 through a fixed contact and a movable contact of a switching circuit 8, a fixed contact a and a movable contact c of a switching circuit 9, a resistor B having a resistance value R and a fixed contact a and the movable contact c of the switching circuit 3, thereby deriving at the output side of amplifier 4 an integrated output produced by positively integrating the reference voltage +V, with the resistor B and the capacitor being used as integration contacts.

Reference numeral 10 identifies a negative reference voltage source, from which a negative reference voltage -V, is fed to the input side of the amplifier 4 through a fixed contact b and the movable contact 0 of 2 the switching circuit 9, the resistor B and the contacts a and c of the switching circuit 3, thereby deriving at theoutput side of the amplifier 4 an integrated output which is produced by negatively integrating the reference voltage V, with the resistor B and the capacitor 5 being used as integration constants.

Reference numeral 11 indicates a zero reference power source, from which a zero voltage V, is supplied to the input side of the amplifier 4 through a fixed contact b and the movable contact 6 of the switching circuit 8, the contacts a and c of the switching circuit 9, the resistor B and the contacts a and c of the switching circuit 3. In this case, however, the voltage V, is zero, so that at the output side of the amplifier 4, neither positive nor negative integration is achieved and the integrated output is not changed.

Reference numeral 12 represents a switch which is connected in parallel to the capacitor -5 for reducing the integrated output to zero.

Reference numeral 13 designates a comparator circuit which is connected to the output side of the amplifier 4 and compares an integrated output V, produced therefrom with the zero reference voltage whether the former is positive (including zero) or negative relative to the'latter. The comparator circuit 13 is adapted to produce a compared output E, which is indicated by 1 or 0 according as the integrated output voltage V, is positive or negative;

Reference numeral 20' identifies a timing signal generator circuit. For convenience of explanation, times in sequential order are indicated by t t t t t 2,, and t-, and periods of time betweenthe times t and between t, and 13,, between and between t, and t.,, be-

tween t and t between t and t and between t, and

' of the level l such as illustrated in FIG. 2-A5 at a terminal U5 between the times and t;,, a rectangular wave ()1 of the level l-such as shown in FIG. 2-A1 at a terminal U1 between the times t,, and t,, a pulse PE The rectangular wave QA is fed to the switching circuit 3 to control it in such a manner that its contact 0 lies on the contact b while the rectangular wave QA is at the level l and that the contact 6 lies on the n t a hil h rect ula wa eis the level The rectangular wave-QB is applied to an OR" circuit 21 and the rectangular waves Q5, Q4, Q3, Q2 and Q1 are respectively supplied to AND circuits G5, G4, G3, G2 and G1. While the rectangular waves Q5, Q4, Q3, Q2 and 01 are respectively fed to set terminals d of flip-flop circuits F5, F4, F3, F2 and F1. These flip-flop circuits F5, F4, F3, F2 and F1 are supplied with the compared output E and when the compared output E is at the level l the flip-flop circuits F5, F4, F3, F2 and F1 are respectively set by the leading edges of the rectangular waves Q5, Q4, Q3, Q2 and Q1, and accordingly outputs H5, H4, H3, H2 and H1 derived at output terminals e of the flip-flop circuits F5 to F1 are indicated by l respectively. When the compared output E is at the level the flip-flop circuits F to F4 are not set by the rectangular waves Q5 to Q1, and accordingly the outputs 1-15 to H1 are indicated by O'!7 The flip-flop circuits F5 to F1 respectively correspond to fifth to first digits of a binary number, so that the outputs 1-15 to H1 represent-a digital output of a binary number having five digits. This digital output is fed to a buffer circuit 22, while the buffer circuit 22 is supplied with the pulse PE obtained at the time t, and

' based upon the pulse PE the digital output represented by the outputs of the flip-flop circuits F5 to F1 is applied to a memory circuit 23. Further, the pulse PE is supplied to reset terminals g of the flip-flop circuits F5 to F1, by which if their outputs H5 to H1 are at the level 1, they are changed to the level 0.

Further, the outputs H5 to H2 are respectively applied to the aforementioned AND circuits G5 to G2, whose outputs J5 to J2 are fed to the OR circuit 21. Then, the output K of the OR circuit 21 is, in turn, supplied to the switching circuit 9 to control it in such a manner that its contact 0 is held on the contact b while the output K is at the level 1 and that the contact 0' lies on the contact a while the output K is at thelevel 0.

While, the output H1 is applied to the aforementioned circuit G1, whose output J1 is fed to the switch-- ing circuit 8 to control it so that its contact c stays on the contact b while the output J1 is at the level l and the contact 0 remains on the contact a while the output J1 is at the level 0."

The rectangular'wave QC is supplied to the switch. 12 I to turn it on while the rectangular wave QC is at the level 1.

, The foregoing hasoutlined the construction of one example of this invention, which will be further described together with its operation. Since the switch 12 is closed by the rectangular wave QC prior to the time t the integrated output V is zero. Assume that the flip-flop circuits F5 to F1 are respectively reset before the time t and accordingly the outputs H5 to 1-11 are respectively at thelevel 0.

Under such conditions, the rectangular wave QC becomes of the l evel"0"at the time t and switch 12, is opened and, further, the rectangular wave QA becomes of the level l so that positive integration of the analog voltage V is initiated with an integrator consisting of the resistor 2, the capacitor 5 and the amplifier 4 and this integration is continued to the'time 1., when the rectangular wave QA be comes of the level 0.

The resistance value of the resistor2 is R, the capacitance of the capacitor 5 is C and the period of time between the times t and t is 2T, so that the above integration is achieved based on the following equation.

- c I 7.11.1 THETHWH 7. V .1 2 I 0.. Ye e 1) AccordinglyQthe'value of the integrated output V, at the time t is VI, (volt) given by. the equation (1). For convenience of explanation, let it be assumed that the value VI, of the equation (1) is +V,,,such as 11001 volts in binary number (25 in decimal number). The integrated output V increases from the zero voltage at the time t to V1, as a value'of l 1001 volts in binary number (25 in decimal number) at the time t as shown in FIG. 2B.

At the time t, the rectangular wave QA becomes of the level 0 and the contact 0 of the switching circuit 3 is turned down to the contact a. While, the rectangular wave QB becomes to the level 1 and is applied to the OR circuit 21, whose output K is becomes to the level 1 to bring the contact 0 of the switching circuit 9 to the contact b. As a result of this, negative integration of the reference voltage V, is initiated with an integrator consisting of the resistor B, the capacitor 5 and the amplifier 4 and this integration is kept on to the time t when the, rectangular wave QB becomes to the level 0.

The resistance value of the resistor B is R, the capacitance of the capacitor 5 is C and the period of time between the times t, and 2 is T, so that the above integration is accomplished based upon the following equa-- tion.

. 'zrah (2) Therefore, the value V1 of the integrated output V at the time t is given as follows:

For the sake of brebity, if the value of ['V, resistance R and capacitance C in the equation (2) are so selected that V is 10000 volts in binary number (16 2 in decimal number), the value of the integrated output V, becomes smaller than 1 1001" volts in binary number (25 in decimal number) at the time t, and has a value such that V1 l 1001- 10000 =0100l (volts) in binary number (V1 =25 16 9 (volts) in decimal number). At the time t 'the rectangular wave QB becomes to the level 0 and the rectangular wave Q5 becomes to the level l While, the integrated output -V, is positive between the times t and t so that the output E of the comparator circuit 13 is at the level l as depicted in FIG. 2D between thetimes t and :2- d n y he flip-fl p ircuitF is ,sstatth m t and its output H5 is changed to the level 1 as depicted in FIG. 2- E5. Asa result of this, the output J5 ofthe AND circuit G5 becomes to the level l as shown in FIG. 2F5 and is applied to the ORTcircuit 21 and its output K becomes to the level l even after the time t so that the contact c of the switching circuit 9 remains on the contact b. Consequently, the reference voltage "Vr is similarly integrated and this integration is continued to the time I when the output J5 is changed to the level 0, since the rectangular wave Q5 becomes to the level 0.3"

The integration in this case 18 carried out based on the following equation.

the level 1 and the integrated output V, remains positive until the time t Accordingly, the output E, of the I comparator circuit 13 is at the level 1, and consequently the flip-flop circuit F4 is set at the time 1 and its output I-I i is changed to the level 1 As a result of this. the output .14 of the AND circuit G4 becomes to the level 1 as depicted in FIG. 2- F4 and the output K of the OR circuit 21 remains at the level 1" even after the time t;, to hold the contact c of the switching circuit 9 on the contact a. Consequently, the reference voltage V, is integrated and this integration continues until the time t, when the rectangular wave Q4 becomes to the level to cause the output J4 to the This integration is achieved based on the following equation By the way, since V is 00100 volts in binary number (4 =2 in decimal number), the integrated output V, becomes smaller than the value of 00001 volts in binary number (1 in decimal number) at the time t as depicted in FIG. 2--B and has a value such that V1 00001 00100 0001 1 volts in binary number (VI 1-4 3 in decimal number) at the time t,.

At the time t the level of the rectangular wave 04 becomes to 0 and that of the rectangular wave Q3 becomes to 1 and the integrated output V, becomes negative at a time t intermediate between thetimes t and Accordingly, the level of the output E, of the comparator circuit 13 becomes 0 at the time and consequently the flip-flop circuit F3 is not set at the time t, and its output H3 is at the level 0 as shown in FIG. 2E3. Therefore, the output J3 of the AND circuit G3 is also at the level 0 as depicted in FIG. 2--F3 and the level of the output K; of the OR circuit 21 becomes 0 at the time t.,. As-a result of this, the contact c of the switching circuit 9, is changed over to its contact a to integrate the reference voltage +V, and this integration continues until the time when the level of the rectangular wave 03 becomes 0.

This integration is accomplished based on the following equation.

Therefore, the value V1 of the integrated output V, at the time t is given as follows:

By the way, since V is 00010 volts in binary number (2 =2 in decimal number), the integrated output V, increases from the value of 0001 1 volts in binary number (3 in decimal number) at the time t, as depicted in FIG. 2-B and has a value such that V1 000ll 00010 00001 volts in binary number (V1 3 2 l in decimal number at the time At the time 2 the rectangular wave Q3 becomes to the level 0 and the rectangular wave Q2 becomes to the level 1. However, the output E,- of the comparator circuit 13 remains at the level 0, so that the flipflop circuit F2 is not set and its output H2 is at the level 0 as shown in FIG. 2E2. Accordingly, the output J2 of the AND circuit G2 is also at the level 0 as depicted in FIG. 2-F2 to hold the output K of the OR circuit at the level 0. As a result of this, the contact 0 of the switching circuit 9 is retained on its contact a and the reference voltage +V, is integrated and this integration is kept on until the time t when the rectangular wave Q2 becomes to the level 0.

This integration is carried out based on the following equation.

Therefore, the value V1 of the integrated output V, is given as follows:

VI, V1 V By the way, since V is 00001 volts in binary number (1 2 in decimal number), the integrated output V, increases from thevalue of 00001 volts (l in decimal number) at the time 1 and has a value such that VI, 00001 00001 00000 volts (V1 l l 0 in decimal number) at the time i At the time t the level of the rectangular wave Q2 becomes to 0 and that of the rectangular wave Q1 becomes to 1. While, the integrated output V, is reduced to zero at-the time 2 so that the output E; becomes to the level 1 at the time l to thereby set the flip-flop circuit Fl. Consequently, the level of the output H1 becomes 1 as shown in FIG. 2E1 and that of the output .11 of the AND circuit G1 also becomes 1. While, the output K of the GR circuit 21 remains at the level 0 after the time 16. And the contact 0 of the switching circuit 8 is changed over to its contact b but the contact 0 of the switching circuit 9 remains on its contact a, so that the zero voltage V is integrated until the time t-,. This integration is accomplished based on the following equation.

Therefore. the value VI of the integrated output V, at the time I, is given as follows:

By the way, since V is zero volt, the value of the integrated output V, remains unchanged and'has a value such that V1 00000 volt at the time t,.

Thus, at the time t, the outputs H5, H4 and'I-Il are.

converter of the construction shown in FIG. 1 in the case where the analog voltage V is 1 1001 in binary.

number (25 in decimal number). FIG. 3 shows the operation of the A-D converter of FIG. 1 in the case where the analog voltage V is 101 in binary number (22" in decimal number). In the present example, the value VI, of the integrated output V, at the time t is 10110 in binary number (22 in decimal'number) based upon the following equation.

FTOJ O VindtVIi At the time t the value VI of the integrated output V, is such thatVh V 10110 10000 =O01 1O (volts) based upon the following equation.

At the time the integrated output V, has such a value V1 that V1,, V 00110 01000 00010 (volts) based upon the following equation. a

At the time 1., the integrated output V, is of such a value At the time it the value V 1 of the integrated output V, is such that V1 V =0O0'l0 00010 00000 (volt) based upon the followingequation.

At the time t the value VI of the integrated output V,

is such that V], V 00000 00001 00001 (volt) based upon the following equation.

At the time t, the value VI of the integrated output V is such that V1 V 00001 00001 00000 (volt) based upon the following equation.

1 E Rel 0) Thus, at the time t, the outputs H5 to H1 are respectively l, 0, 1, l and 0 and they are applied through the buffer circuit 22 to the memory circuit 23 based upon the pulse PE at the time t and memorized in the memory circuit. Accordingly, it is known that the analog voltage V is 10110 volts in binary number (22 in decimal number).

The foregoing description has been given in connection with the cases where the analog voltage V,-,, is

11001 and 101 10 in binary number and so long as the analog voltage is less than 10000 volts in binary number (32 in decimal number), the analog voltage V, can be obtained in the form of a digital output of five digits in binary number. Further, the foregoing description' has been given of the case where the analog voltage V, is positive but it will be seen that when the analog voltage is negative, too, exactly the same results can be obtained, if the output E of the comparator circuit 13 can be obtained in the opposite polarity to that in the foregoing. v

Referring now to FIG. 4, another embodiment of this invention .will hereinafter be described. The present example is identical in construction with that of FIG. 1 except that a parallel circuit consisting of resistors B16, B8, B4, B2 and B1 respectively having resistance values R, 2R, 4R, SR and 16R is used in place of the resistor B in FIG. 1, that switches D16, D8, D4, D2 and D1 are connected in series with these resistors B16, B8, B4, B2

. and B1, that the time intervals between the signals produced by the timing signal generator circuit 20, namely the periods of time between the times t and 2 between and t and between t and t, are equally T, that the resistance value of the r'esistor2 is R/2, that the switches D16, D8, D4 and D2 are respectively controlled bythe rectangular waves QB, Q5, Q4 and Q3 to be closed when the rectangular waves are at the level 1 and that the switch D1 is controlled by the rectangular waves 02 and Q1 derived from the OR circuit 24 to be closed when the rectangular waves are at the level 1'." Accordingly, elements corresponding to those in FIG. 1 are identified by the same reference numerals and characters and will not be described further. In the event that the. analog voltage V,-,, is 1 1001 in binary number asabove described, the values VI V1 V1 V1 V1 V1 and Vl bf the integrated outputs V, at the times t t t t t and respectively become 11001,. 01001, .00001, .00011,",00001,. 00000 and 900000 volts, based upon the following integration equations, as depicted in FIG. 5.

T I }j; V clt=VI (21) T REL (22) 1 I V dt V 2R0 o B (23) 1 TV dt V 24 1 Vdt V mi) (2 VdV lfiRC-jii 1 2 1 T i 1.66. f0 ME? (27) As a result it is known that the analog voltage V5,, is 11001 as in FIG. 1. y

In the event that the analog voltage V is 10110, the values VI V1 VI V1 VI VI and VI of the integrated outputs V, at the times t t t t t t and t respectively become 10110, 00l 10, 00010," 00010, 00000, 00001and 00000 volts, based upon the following equations, as shown in FIG. 6.

T i-f V dt=VI As a result, it is known that the analog voltage V, is 10110 as in FIG. 1.

Turning now to FIG. 7, a further modified form of this invention will hereinbelow be described. The present example is similar in construction to that of FIG. 1 except in that terminals M M M and M for respectively obtaining voltages (+V,/2), (+V /4), (-l-V /8 and (+V ll6) are provided in the power source 7 in addition to the terminal M of the voltage +V and are con nected to the contact a of the switching circuit 8 through switches D16, D8, D4, D2 and D1 respectively, that terminals M' M M and M for respectively obtaining voltages (V /2), (V,/4), (V,/8) and (*V,/l6) and provided in the power source 10 in addition to the terminal M' of the voltage -V,. and are connected to the contact b of the switching circuit 9 through switches D16, D8, D4, D2 and D1, that the switches D16, and D16, D8 and D8, D4'and D4 and D2 and D2 arev respectively controlled by the rectangular waves QB, Q5, Q4 and O3 to be closed when the rectangular waves are at the level l that the switches D1 and D1 are controlled by the rectangular waves Q2 and Q1 derived from the OR circuit 24 tobe closed when the rectangular waves are at the level 1, that the resistance value of the resistor 2 is R'/ 2 and that the time intervals of the signals derived from the timing signal generator circuit 20, namely the periods of time between the times t and t between 1 and r and between t and t, are all equally T. Accordingly, elements corresponding to those in FIG. 1 are identified by the same reference numerals and characters and will now be described further. In the case where the analog voltage V,-, is "l in binary number. the values Vli. V1 VIN. V13. Vb. VI, and Vl of the integrated outputs Vs at the times 11. I 13. t4. I5. I and I respectively become 1 I001 0100i. 0000] 0001 l I 00001 00000 and 00000" volts.

based upon the following equations. as depicted in FIG) 5.

T J-f Vi dt=VI As a result, it is known that the analog voltage V,- is 11001 as in FIG. 1.

Further, where the analog voltage V n is 101 10 the values Vl,-, V1 V1 V1 V1 VI and VI of the outputs at the times t,, t t t t t and 2, respectively become 10110, 00110, 000l0,000l0, 00000, O000l and .00000, based upon the following equations, as depicted in FIG. 6.

T f Vi dt=VI As a result, it isknown that the analog voltage V,- is 10110 as in FIG. 1.

Although the foregoing examples of this invention have been described in connection with the case where the analog voltage is obtained in the form of a binary number of five digits, it will be apparent to those skilled in the art that a digital output of any desired number of digits more than one digit can be obtained.

Whilethe foregoing description has been given in connection with the cases where the resistance values and the voltage are held constant and the ratios of the a time intervals of the timing signals are sequentially selected 1: /z:% where the time intervals of the timing signals and the voltage are held constant and the ratios of the resistance values are sequentially selected 1:2:4 and where the time-intervals of the timing signals and the resistance values are held constant and the ratios of the reference voltages are respectively selected 11 /294 and the ratios of the amounts of integration areobtained as 16:8:4 it will be seen that the same results as those in the foregoing can be obtained by selecting at suitable ratios of the voltage and the time interval with only I the resistance value being constant, at suitable ratios of the time interval and the resistances with only the voltage being constant, or at suitable ratios of the resistances and the voltage with only the time interval in such a mannerthat the ratios of the amounts of integration are obtained as 16:8:4 It is also possible to select the resistance. the time intervals and the voltages at suitable ratios. I

Although the foregoing description has been given of the case where the analog voltage V is integrated between t and t It will be apparent that many modifications and variations may be effected without departing from the scope of the novel concepts of this invention.

I claim as my invention:

1. An integrating A-D conversion method for converting an analog input voltage into a digital output in the form of a binary number having 11 digits consisting of first, second, third (n 1 )th and nth digits, which comprises the sequential steps A A A A A A and B;

I A integrating a positive (or negative) analog input voltage by integrating means for a predetermined period of time;

" A integrating a negative (or positive) reference voltage by the integrating means for a periodof time T and storing a digital signal 1 (or O) in a first storage means when an output derived from the integrating means at the end of the step A is positive (or negative); I

- A integrating the negative (or positive) reference voltage by the integrating means for a period of S time 2T/(2 and storing a digital signal 1" (or 0) in a second storage means when an output derived from the integrating means at the end of the step A, is positive (or negative);

A integratingthe negative (or positive) reference voltage by the integrating means for a period of time 2T/(2 and storing a digital signal 1 (or O") in a third storage means when an output derived from the integrating means at the end of the step A; is positive (or negative);

A 1: integrating the negative (or positive) reference voltage by the integrating means for a period of time 2T/(2)" and storing a digital signal 1 (or 0f) in an (n -l )th storage means when an output derived from the integrating means at the end of the step A is positive (or negative); A integrating the negative (or positive) reference voltage by the integrating means foria period of time ,2T/(2)" and storing a digital signal 1" (or 0) in a nth storage means when an output derived from the first integrating means at the end of the step A,, is positive (or negative); B: applying the digital signals stored in the first, second, third, (n-l )th and nth storage means to an output "storage circuit to store them therein; thereby providing a digital output in the form'of a binary number having n digits consisting of the first, second, third, (n-l )th, and nth digits in order of significance stored-in the storage'circuit.

2. A method of converting an analog input voltage into a digitaloutput according to claim 1, in which the change of charge during each step is determined by integrating a fixed'magnitude reference voltage of polarity inverse to the charge remaining after the preceding 

1. An integrating A-D conversion method for converting an analog input voltage into a digital output in the form of a binary number having n digits consisting of first, second, third . . . (n -1)th and nth digits, which comprises the sequential steps A0, A1, A2, A3, . . . A(n-1), An and B; A0: integrating a positive (or negative) analog input voltage by integrating means for a predetermined period of time; A1: integrating a negative (or positive) reference voltage by the integrating means for a period of time T and storing a digital signal ''''1'''' (or ''''0) in a first storage means when an output derived from the integrating means at the end of the step A1 is positive (or negative); A2: integrating the negative (or positive) reference voltage by the integrating means for a period of time 2T/(22) and storing a digital signal ''''1'''' (or ''''0'''') in a second storage means when an output derived from the integrating means at the end of the step A2 is positive (or negative); A3: integrating the negative (or positive) reference voltage by the integrating means for a period of time 2T/(23) and storing a digital signal ''''1'''' (or ''''0'''') in a third storage means when an output derived from the integrating means at the end of the step A3 is positive (or negative); . . . . . . . . A -1: integrating the negative (or positive) reference voltage by the integrating means for a period of time 2T/(2)n-1 and storing a digital signal ''''1'''' (or ''''0'''') in an (n -1)th storage means when an output derived from the integrating means at the end of the step An-1 is positive (or negative); An: integrating the negative (or positive) reference voltage by the integrating means for a period of time 2T/(2)n and storing a digital signal ''''1'''' (or ''''0'''') in a nth storage means when an output derived from the first integrating means at the end of the step An is positive (or negative); B: applying the digital signals stored in the first, second, third, . . . (n-1)th and nth storage means to an output storage circuit to store them therein; thereby providing a digital output in the form of a binary number having n digits consisting of the first, second, third, (n-1)th, and nth digits in order of significance stored in the storage circuit.
 2. A method of converting an analog input voltage into a digital output according to claim 1, in which the change of charge during each step is determined by integrating a fixed magnitude reference voltage of polarity inverse to the charge remaining after the preceding step for a time interval that is one half the time interval of the preceding step.
 3. A method of converting an analog input voltage into a digital output according to claim 1, in which the change of charge during each step is determined by integrating for a fixed time a fixed magnitude reference voltage of polarity inverse to the charge remaining after the preceding step through an integrator resistor the resistance of which is doubled for each succeeding step. 